Booth Encoded Multiplier
2019
This project was assigned to every couple student in VLSI-I lab. First, I designed the complete schematic diagram in Cadence. Then I verified the multiplication result using different input binary numbers. After that, the most daunting task was to design the CMOS layout. It took many hours to design everything starting from scratch. I had to start from basic gates (NOT, NAND, NOR)Â and then combine them to build a block such as- encoder, half adder etc. The final layout was approved by the course teacher.
Brief Description
This is the complete layout of the multiplier circuit. It consists of several blocks such as- booth encoder, booth decoder, sign extension block, half adder, ripple carry adder etc. All these blocks are generated from basic logic gate units (NOT, NAND2, NAND3, XOR2 etc).
